1. Field of the Invention
The present invention generally relates to monolithic integrated circuits, and, more particularly, to a spiral inductor having two stacked inductor spirals with the same direction of current flow.
2. Description of the Prior Art
Many digital and analog circuits, including complex microprocessors and operational amplifiers, have been successfully implemented in silicon based integrated circuits (ICs). These circuits typically include active devices such as bipolar transistors and field effect transistors (FETs), diodes of various types, and passive devices such as resistors and capacitors.
Attempts to miniaturize radio frequency (RF) circuits, however, remain a challenge. RF circuits are used in cellular phones, wireless modems, and other types of communication equipment. The miniaturization problem arises due to the difficulty in producing a good conductor in silicon technologies which is suitable for RF applications at widely used microwave frequencies from 900 MHz to 2.4 GHz.
Monolithic microwave integrated circuits (MMICs) are rapidly outpacing discrete integrated circuits in mobile wireless communications products, as described in R. Schneiderman, "Who's winning the wireless war?", Microwave & RF, October 1994, pp. 31-36. MMICs require high-Q passive components, such as inductors and capacitors, to be able to realize integrated filters and matching sections with small insertion losses.
If conventional silicon technology is used, e.g., BiCMOS, the inductor is clearly the performance and density limiting passive element. While the Q of an integrated inductor can be improved by modifying the interconnect technology by switching from AlCu to Cu or Au interconnects, the area consumption of the inductor structure is difficult to reduce. For example, a single inductor of 2 nH inductance would encompass an area of approximately 250.times.250 .mu.m.sup.2.
It is well known that the direct current (DC) resistance of a metal line that forms a spiral inductor is a major contributor to the inductor Q degradation. One way to reduce this effect is to use wide metal line widths. However, this increases the inductor area and the parasitic capacitance associated with the structure. The larger inductor area limits the miniaturization that can be achieved, and the parasitic capacitance associated with the larger area decreases the self-resonance frequency of the inductor, thereby limiting its useful frequency range.
Further, since the Q is directly proportional to the frequency and inversely proportional to the series loss of the inductor, the metal line widths cannot be chosen arbitrarily.
Attempts to integrate inductors into silicon technologies have yielded either inductor Q values of less than five or required special metalization layers such as gold.
A standard feature in present day very large scale integration (VLSI) is the use of multi-level interconnects for inductor integration. Using this technology in an effort to provide a high-Q circuit, some have shunted several layers of metal together to "simulate" a thicker metal layer than achievable in AlCu interconnect technology. See U.S. Pat. No. 5,446,311 to Soyuer et al., issued Aug. 29, 1995 (assigned to IBM). With Q values above five, such shunted inductors represented an improvement over the prior art. Efforts continue, however, to manufacture inductors with even higher Q values.
In light of the foregoing, there exists a need for monolithic inductor structure having Q values well in excess of five that can be integrated at radio and microwave frequencies.